The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a saddle fin-shaped channel and a method for manufacturing the same.
Trends in the semiconductor industry have lead to a decrease in the design rule of a semiconductor device. This decrease has made it difficult to achieve the desired target threshold voltage when using a conventional planar channel structure. A semiconductor device with a three-dimensional channel structure has been suggested as a device with potential for overcoming the problems associated with the convention planar channel structure. Examples of a semiconductor device having a three-dimensional channel structure include semiconductor devices having a recess channel or a protrusion channel. Another such semiconductor device is the semiconductor device having a saddle fin-shaped channel, in which the recess channel and the protrusion channel are combined.
When compared to a conventional semiconductor device having a planar channel structure, the semiconductor device having the saddle fin-shaped channel realizes an increase in the effective channel length and an obtainable target threshold voltage. As a result of the increase in the effective channel width, current drivability can also be improved.
The semiconductor device having the saddle fin-shaped channel is structured such that the gate forming area in the active region is recessed to a first depth, and portions of an isolation layer which extend away from the gate forming area in the active region are recessed to a second depth greater than the first depth to expose front and rear surfaces of the gate forming area recessed to the first depth.
However, the isolation layer of the semiconductor device having the saddle fin-shaped channel comprises an oxide layer, and therefore; a pre-cleaning process is typically conducted immediately prior to forming the gate oxide layer using an HF solution. In this regard, enlargement of the recess pattern defined in the isolation layer is likely due to etch loss caused during the pre-cleaning process.
As a consequence, during a subsequent landing plug contact (LPC) process, the active region and the isolation layer can be etched together in the area where the plug of a bit line node is formed. Due to this fact, a self-align contact (SAC) fail, such as bridging between a gate pattern and an LPC plug, can occur, thereby leading to a decrease in manufacturing yield.
Therefore, in order to manufacture the semiconductor device having the saddle fin-shaped channel, it is necessary to prevent bridging between the gate pattern and the LPC plug.